The following is a translation of Shiozawa's FADC board spec sheet he
sent to vendors.
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(1) Summary
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A flash ADC periodically/continually digitizes analog signals and
measures charge in each unit of time it operates.  The digitized
signal is saved to on-board memory.  These operations continue until a
stop signal is sent.

(2) Specifications
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o Operating Speed  | 500 MHz
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o Input Frequency  | > 500 MHz
  Range            |
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o Number of Input  | Approximately 10 channels per board.  Want to make as
  Channels:        | dense as possible.
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o Input Voltage    | Approximately 0 - 1 Volts (negative input)
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o Input Impedance  | 50 Ohms
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o Charge           | > 8 bits, linear ADC 10 bits
  Measurement      |
  Precision        |
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o Input Time       | 1 microseconds per trigger
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o On-board memory  | Enough to hold 1 microseconds of data (500 bytes/channel x
  capacity         | # channels x 100(?))
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o Dead Time        | Want < 10% dead time at 100 Hz (< 1ms processing time per
                   | event).  Possibly want 2 FADCs per channel to make dead-
                   | time free operation.
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o Trigger          | Pre-trigger: Save signals before trigger signal arrives.
                   | Combine signals from all channels and apply trigger.
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o Clock            | Use on-board jumpers to adjust the data input rate.  Also
                   | want external clock input.
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o Zero Suppression | Do pedestal subtraction on board.  Pedestal values 
                   | downloaded from external computer.
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o Bus Interface    | VME?  Must support block transfers.
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