VFI scope pictures

Struck Stop Trigger (STRG) output vs. Global Trigger input:
chan.1:
Global Trigger input signal, measured at the Lemo connector J2 (NIM-level),
chan.2:
STRG signal, measured at the monitor output (Lemo connector J6, NIM-level).
Here, the STRG pulse width was set to 100 nsec. The scope was set to "infinite persistence" mode in order to plot multiple measurements in one single graph. As shown, the leading edges of the STRG pulse follow (unvetoed) Global trigger pulses after a delay of approx. 40...60 nsec. The 20 nsec variation is due to the 50 MHz sampling rate.
Struck Stop Trigger (STRG) vraiable pulse width range:

Same scope setup as above.
Here, the STRG pulse width was set to all 15 possible variable settings (rotary switch S2) during the test period, i.e. from 20 nsec to 300 nsec in 20 nsec steps.

TDC Common Stop Trigger (FTRG) output vs. Global Trigger input:
chan.1:
Global Trigger input signal, measured at the Lemo connector J2 (NIM-level),
chan.2:
FTRG signal, measured at the monitor output (Lemo connector J8, NIM-level).
Example 1: minimal delay setup..
The digital delay of the FTRG signal was set via DIP switch S1 to minimal, with switch settings:
0100 110000
As shown, the propagation delay of the circuit is approx. 60...80 nsec, where the 20 nsec variation is due to the 50 MHz sampling clock.
Example 2 of FTRG vs. Global Trigger signals: 2 µsec delay.

Same scope setup as above, but DIP switch S1 set to 2.00 µsec:

1100 100100

As shown, the delay measured at the FTRG monitor connector is approx. 2.012 µsec +/- 10 nsec.

Example 3 of FTRG vs. Global Trigger signals: 8 µsec delay.

Same scope setup as above, but DIP switch S1 set to 8.00 µsec:

1111 110110

As shown, the delay measured at the FTRG monitor connector is approx. 8.013 µsec +/- 10 nsec.

Example 4 of FTRG vs. Global Trigger signals: 16 µsec delay.

Same scope setup as above, but DIP switch S1 set to 16.00 µsec:

1111 001011

As shown, the delay measured at the FTRG monitor connector is approx. 16.016 µsec +/- 10 nsec.

Example 5 of FTRG vs. Global Trigger signals: maximum delay setting.

Same scope setup as above, but DIP switch S1 set to 19.50 µsec:

0111 111111

As shown, the delay measured at the FTRG monitor connector is approx. 19.517 µsec +/- 10 nsec.

Pulse sequences during bursts of Global Trigger pulses:
ch.4:
(top) Global Trigger at the Lemo input connector J2 (NIM-level),
ch.2:
(2nd from top) Combined TDC busy signal (BIP-OR), measured at the Lemo connector J4 (TTL-level),
ch.1:
(2nd from bottom) Trigger reference signal (T0) for the "event number splitter", measured at the modular connector JP1 of the FCM board, including local BIP-veto circuitry, (RS485/TTL level),
ch.3:
(bottom)Struck Stop Trigger (STRG), measured at Lemo connector J6 (NIM-level).
As shown, the first non-vetoed Global Trigger pulse is used to generate a Stop Trigger (STRG) pulse for the Struck latches. Immediatedly after the STRG generation, the delay counter for the FTRG pulse generation (not shown here) is started. In this case, the delay was set to 16 µsec.

Approx. 500 nsec after the FTRG pulse generation (thus approx. 16.5 µsec after the STRG pulse, TDC busy signals are arriving through the cables from the outer huts to the VFI board and generate a BIP veto signal. In this example, the combined BIP signal is approx. 9 µsec long.

From the start of the FTRG delay counter activity until the end of the corresponding TDC BIP signals (in this example approx. 26 µsec), there are no further STRG pulses generated. I.e. all incoming Trigger pulses during that period are vetoed, as clearly shown in the picture.

At channel 1 it can be seen that the reference trigger signals for the "event number splitter" (TDC data) is vetoed whenever one of the TDCs is in busy state, i.e. the combined BIP signal is logic high.

back to the main page