/*************************************************************************/
/*  VFI_ADDR.TDL                                                         */
/*                                                                       */
/*  Address logic for the VME-FASTBUS INTERFACE (VFI) for the VME        */
/*  electronics of the SuperK OD DAQ.  Works parallel with the address   */
/*  logic for the FAN-IN/OUT AND CALIBRATION MODULE (FCM) in the same    */
/*  crate.  It checks the VME bus for the following conditions:          */
/*                                                                       */
/*    AS (Address Selector)    = 0                                       */
/*    WR (Write/Read flag)     = 0  (=write)                             */
/*    AM0..5 (Addr. Modifier)  = 29 (hex)                                */
/*    Addresses:                                                         */
/*      FSCC Reset pulse hut 1 = D1xx (hex)                              */
/*      FSCC Reset pulse hut 2 = D2xx (hex)                              */
/*      FSCC Reset pulse hut 3 = D3xx (hex)                              */
/*      FSCC Reset pulse hut 4 = D4xx (hex)                              */
/*      Reset Veto for Trigger = D5xx (hex) (set/unset with data bit D0) */
/*      DTACK reply            = D000...D7FF (hex)                       */
/*************************************************************************/

#define  PALNAME VFI_ADDR
#define  JEDFILE "VFI_ADDR.JED"
#define  PALTYPE "g26cv12"
#define DESIGNER H.G. Berns
#define  COMPANY SuperK group, UW-Physics, Seattle
#define  PARTNUM G26CV12
#define REVISION V1.0 (last: July 9, 1996)
#define COMMENTS \
        VFI address selector logic (D0xx...D7FF)

/************ I/O definitions ********************************************/
                                                                         
PALNAME  (in  regclk,       /* clock input for register output(s)        */
              reset,        /* clear signal for register(s) (test only)  */
              a15..8,       /* VME bus address bits 8-15                 */
              !as,          /* Addr. Select from VME bus                 */
              !wr,          /* Read/Write flag from VME bus              */
              am1..0;       /* Addr. Modifier bits 0+1                   */
          io  am5..2,       /* Addr. Modifier bits 2-5                   */
              d0,           /* data bit D0                               */
              dtack,        /* DTACK output to VME bus                   */
              str,          /* strobe for RVETO register clock           */
              fr4..1;       /* pulses for the FSCC resets                */
          reg rveto)        /* register output for Reset Trigger Veto    */

/************ PLD equations **********************************************/
{
    group ad[a15..8], am[am5..0], ins[am5..2,d0], outs[fr4..1,str,rveto],
          ad3[a15..11];
    
    rveto.ck   = regclk;    /* hook up register clock                    */
    rveto.pre  = 0;         /* register preset                           */
    rveto.aclr = reset;     /* register clear                            */
    outs[].oe  = ~0;        /* enable active outputs                     */
    ins[].oe   = 0;         /* select I/O's as input only                */

    dtack = 0;

    fr1 = as & wr & am[]==41 & ad[]==209;           /* Addr = D100..D1FF */
    fr2 = as & wr & am[]==41 & ad[]==210;           /* Addr = D200..D2FF */
    fr3 = as & wr & am[]==41 & ad[]==211;           /* Addr = D300..D3FF */
    fr4 = as & wr & am[]==41 & ad[]==212;           /* Addr = D400..D4FF */
    
    str = as & wr & am[]==41 & ad[]==213;           /* Addr = D500..D5FF */
    
    rveto = d0;             /* register = value of D0 at STR strobe      */

    dtack[].oe = as & wr & am[]==41 & ad3[]==26;    /* Addr = D000..D7FF */

/************ PLD part definition ****************************************/
    
    putpart(PALTYPE, JEDFILE,
    regclk,    a8,    a9,   a10,   a11,   a12,   VCC,
       a13,   a14,   a15,    as,    wr,   am0,   am1,
       am2,   am3,   am4,   am5,    d0, rveto,   GND,
       fr4,   fr3,   fr2,   fr1, dtack,   str, reset);

/************ Test vector(s) *********************************************/

    test (reset, regclk, ad[], am[], as, wr, d0 => 
          fr1, fr2, fr3, fr4, str, rveto, dtack) {
       tracef("%w %w %3d %2d %w %w %w => %w %w %w %w %w %w %w",
              reset, regclk, ad[], am[], as, wr, d0,
              fr1, fr2, fr3, fr4, str, rveto, dtack);

       (1,?,  0, ?,?,?,? => 0,0,0,0,0,0,\Z); /* init */

       (0,?,  ?, 0,?,?,? => _,_,_,_,_,_, _); /* Addr. mod. not equal 0x29 */
       (_,_,  _, ?,1,?,_ => _,_,_,_,_,_, _); /* AS = 1 */
       (_,?,  ?, ?,?,1,_ => _,_,_,_,_,_, _); /* WR = 1 */
       
       (_,0,206,41,0,0,_ => _,_,_,_,_,_, _);
       (_,_,207, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,208, _,_,_,_ => _,_,_,_,_,_, 0); /* D0xx ==> set DTACK */
       (_,_,209, _,_,_,_ => 1,_,_,_,_,_, _); /* D1xx ==> FR1       */
       (_,_,210, _,_,_,_ => 0,1,_,_,_,_, _); /* D2xx ==> FR2       */
       (_,_,211, _,_,_,_ => _,0,1,_,_,_, _); /* D3xx ==> FR3       */
       (_,_,212, _,_,_,_ => _,_,0,1,_,_, _); /* D4xx ==> FR4       */
       (_,_,213, _,_,_,_ => _,_,_,0,1,_, _); /* D5xx ==> STR       */
       (_,1,  _, _,_,_,1 => _,_,_,_,_,1, _); /*  -> regclk -> RVETO=D0=1 */
       (_,_,  _, _,_,_,? => _,_,_,_,_,_, _);
       (_,_,214, _,_,_,_ => _,_,_,_,0,_, _);
       (_,0,215, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,216, _,_,_,_ => _,_,_,_,_,_,\Z); /* D8xx ==> unset DTACK */
       (_,_,217, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,218, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,219, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,220, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,221, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,213, _,_,_,_ => _,_,_,_,1,_, 0);
       (_,1,  _, _,_,_,0 => _,_,_,_,_,0, _); /*  -> regclk -> RVETO=D0=0 */
       (_,_,250, _,_,_,? => _,_,_,_,0,_,\Z);
       (_,0,251, _,_,_,_ => _,_,_,_,_,_, _);
       (_,_,252, _,_,_,_ => _,_,_,_,_,_, _);
    }                     
}

/************ end of TDL file *********************************************/