/*************************************************************************/ /* UARTCTRL.TDL */ /* */ /* UART control logic for RS232VME module */ /*************************************************************************/ #define PALNAME UARTCTRL #define JEDFILE "UARTCTRL.JED" #define PALTYPE "p22v10" #define DESIGNER H.G.Berns #define COMPANY U.Wash, Seattle - Particle Astrophysics Group #define PARTNUM P22V10 #define REVISION V1.00 (02/12/99) #define COMMENTS UART control logic for RS232VME module /************ I/O definitions ********************************************/ PALNAME (in clk, /* Pin 1 register clock (307.2 kHz) */ set2..0, /* Pin 2-4 user control inputs */ dr, /* Pin 5 UART data received (DR) */ tbre, /* Pin 6 UART trans. buf. reg. empty (TBRE) */ tre, /* Pin 7 UART transmit reg. empty (TRE) */ !ef, /* Pin 8 FIFO empty flag */ reset; /* Pin 13 initializing reset for simulation */ io !frst, /* Pin 22 FIFO reset */ urst, /* Pin 23 UART reset */ freq; /* Pin 17 UART clock signals TRC and RRC */ reg rh, /* Pin 21 internal help register */ !drr, /* Pin 20 UART data received reset (DRR) */ !fread, /* Pin 19 FIFO read */ !tbrl, /* Pin 18 UART transmit buf.reg. load (TBRL) */ rs2..0) /* Pin 14-16 internal clk div. registers */ /************ PLD equations **********************************************/ { group qo[frst, urst, rh, drr, fread, tbrl, freq, rs2..0], qr[rh, drr, fread, tbrl, rs2..0], rs[rs2..0], state[rh, fread, tbrl], fset[set1..0]; #define STATE_A 0b100 /* RH=1 FREAD=0 TBRL=0 (4) */ #define STATE_B 0b110 /* RH=1 FREAD=1 TBRL=0 (6) */ #define STATE_C 0b111 /* RH=1 FREAD=1 TBRL=1 (7) */ #define STATE_D 0b010 /* RH=0 FREAD=1 TBRL=0 (2) */ #define STATE_0 0b000 /* RH=0 FREAD=0 TBRL=0 (0) */ #define STATE_C2 0b011 /* = same as STATE_C (3) */ #define STATE_E1 0b001 /* invalid state 1 (1) */ #define STATE_E2 0b101 /* invalid state 2 (5) */ #define TSTATE_A 0b111 /* test states (FREAD and TBRL inverted) */ #define TSTATE_B 0b101 #define TSTATE_C 0b100 #define TSTATE_D 0b001 #define TSTATE_0 0b011 #define SELECT_A 0b00 #define SELECT_B 0b01 #define SELECT_C 0b10 #define SELECT_D 0b11 qo[].oe = ~0; qr[].ck = clk; qr[].pre = 0; qr[].aclr = reset; frst = set2; /* FIFO reset by user input */ urst = set2; /* UART reset by user input */ drr = dr; rs[]++; /* 3-bit frequency divider for baud rate select */ switch( state[] ) { case STATE_0: /* waiting for new FIFO data + UART ready */ if (tbre & !ef) state[] = STATE_A; else state[] = STATE_0; break; case STATE_A: /* read FIFO data */ state[] = STATE_B; break; case STATE_B: /* write data to UART transmitter buffer */ state[] = STATE_C; break; case STATE_C: /* keep FIFO data valid */ state[] = STATE_D; break; case STATE_D: /* close up shop */ state[] = STATE_0; break; case STATE_C2: /* error state, but same as STATE_C */ state[] = STATE_D; break; case STATE_E1: /* invalid state => reset to STATE_0 */ state[] = STATE_0; break; case STATE_E2: /* invalid state => reset to STATE_0 */ state[] = STATE_0; break; } switch( fset[] ) { case SELECT_A: /* FREQ = clk => 19200 baud (*16) */ freq = clk; break; case SELECT_B: /* FREQ = clk / 2 => 9600 baud (*16) */ freq = rs0; break; case SELECT_C: /* FREQ = clk / 4 => 4800 baud (*16) */ freq = rs1; break; case SELECT_D: /* FREQ = clk / 8 => 2400 baud (*16) */ freq = rs2; break; } /************ PLD part definition ****************************************/ putpart(PALTYPE, JEDFILE, clk, set0, set1, set2, dr, tbre, tre, ef, _, _, _, GND, reset, rs0, rs1, rs2, freq, tbrl, fread, drr, rh, frst, urst, VCC) { neg(frst, drr, fread, tbrl); } /************ Test vector(s) ********************************************/ test (clk, reset, ef, tre, tbre => state[], fread, tbrl) { tracef("%w %w %w %w %w => %d %w %w", clk, reset, ef, tre, tbre, state[], fread, tbrl); ( ?,1,?,?,? => TSTATE_0,1,1); /* init */ (\C,0,0,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,1,_,1 => TSTATE_A,_,_); (\C,_,_,_,_ => TSTATE_B,0,_); (\C,_,0,_,_ => TSTATE_C,_,0); (\C,_,_,_,_ => TSTATE_D,_,1); (\C,_,1,_,_ => TSTATE_0,1,_); (\C,_,_,_,0 => _,_,_); (\C,_,_,_,1 => TSTATE_A,_,_); (\C,_,_,_,_ => TSTATE_B,0,_); (\C,_,_,_,_ => TSTATE_C,_,0); (\C,_,_,_,_ => TSTATE_D,_,1); (\C,_,_,_,0 => TSTATE_0,1,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,1 => TSTATE_A,_,_); (\C,_,_,_,_ => TSTATE_B,0,_); (\C,_,0,_,_ => TSTATE_C,_,0); (\C,_,_,_,_ => TSTATE_D,_,1); (\C,_,_,_,_ => TSTATE_0,1,_); (\C,_,_,_,0 => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,1 => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,1,_,_ => TSTATE_A,_,_); (\C,_,_,_,_ => TSTATE_B,0,_); (\C,_,_,_,_ => TSTATE_C,_,0); (\C,_,_,_,_ => TSTATE_D,_,1); (\C,_,_,_,0 => TSTATE_0,1,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,_ => _,_,_); (\C,_,_,_,1 => TSTATE_A,_,_); } test (clk, reset, dr => drr) { tracef("%w %w %w => %w", clk, reset, dr, drr); ( ?,1,? => 1); /* init registers (test) */ (\C,0,0 => 1); (\C,_,1 => 0); } test (clk, reset, fset[] => rs[], freq) { tracef("%w %w %d => %d %w", clk, reset, fset[], rs[], freq); (?,1,? => 0,?); /* init registers (test) */ (0,0,0 => 0,0); (1,_,_ => 1,1); (0,_,_ => _,0); (1,_,_ => 2,1); (0,_,_ => _,0); (1,_,_ => 3,1); (0,_,_ => _,0); (1,_,_ => 4,1); (0,_,_ => _,0); (1,_,_ => 5,1); (0,_,_ => _,0); (1,_,_ => 6,1); (0,_,_ => _,0); (1,_,_ => 7,1); (0,_,_ => _,0); (1,_,_ => 0,1); (0,_,1 => _,0); (1,_,_ => 1,1); (0,_,_ => _,_); (1,_,_ => 2,0); (0,_,_ => _,_); (1,_,_ => 3,1); (0,_,_ => _,_); (1,_,_ => 4,0); (0,_,_ => _,_); (1,_,_ => 5,1); (0,_,_ => _,_); (1,_,_ => 6,0); (0,_,_ => _,_); (1,_,_ => 7,1); (0,_,_ => _,_); (1,_,2 => 0,0); (0,_,_ => _,_); (1,_,_ => 1,_); (0,_,_ => _,_); (1,_,_ => 2,1); (0,_,_ => _,_); (1,_,_ => 3,_); (0,_,_ => _,_); (1,_,_ => 4,0); (0,_,_ => _,_); (1,_,_ => 5,_); (0,_,_ => _,_); (1,_,_ => 6,1); (0,_,_ => _,_); (1,_,_ => 7,_); (0,_,3 => _,_); (1,_,_ => 0,0); (0,_,_ => _,_); (1,_,_ => 1,_); (0,_,_ => _,_); (1,_,_ => 2,_); (0,_,_ => _,_); (1,_,_ => 3,_); (0,_,_ => _,_); (1,_,_ => 4,1); (0,_,_ => _,_); (1,_,_ => 5,_); (0,_,_ => _,_); (1,_,_ => 6,_); (0,_,_ => _,_); (1,_,_ => 7,_); (0,_,_ => _,_); (1,_,_ => 0,0); } test (set2 => frst) { tracef("%w => %w", set2, frst); (0 => 1); (1 => 0); } } /************ end of CCB_UART.TDL ***************************************/