Local Time Clock version 6 (LTC6)

Custom VME board for SuperK/K2K/WALTA

• 50 MHz reference clock with 32-bit clock counter (= Local Time)
• 4 trigger inputs (+ 5th optional input)
• Event Number and various status flag signal inputs via add-on module
• 64-bit x 4K Event FIFO buffer: each trigger latches Local Time, Event Number, trigger and status flags for readout via VME bus
• VME A24/D16 mode, address modifiers 0x09, 0x0d, 0x39, or 0x3d
• GPS receiver (piggy-back module): Motorola UT-plus Oncore
• UART and FIFO buffer for GPS serial data transfer to/from VME bus

front panel

Inputs and Outputs Name I/O level where function GPS ANT input antenna BNC Antenna signal for Motorola GPS receiver module 1PPS OUT outputs TTL LEMO 1-pulse-per-second timing signal from Motorola GPS receiver; 2 identical 50-Ohm TTL driver outputs SERIAL PORT I/O RS232 DB-9 serial port for monitoring or external control of the Motorola GPS receiver FIFO FULL output TTL LEMO monitoring output for Event FIFO buffer TEST OUT output TTL LEMO fan-out of the TRG0 signal (50-Ohm TTL driver) TRG0,...,TRG3 inputs NIM/TTL LEMO 4 independent trigger inputs; signal level (TTL/NIM) can be set via jumpers behind each LEMO connector TRG4 input TTL header (internal) optional 5th trigger input; normally the header (JP8) is jumpered to provide a 5th trigger via the Event Number bus (from the SuperK trigger system) Ext. CLK input NIM LEMO External 50 MHz clock input, can be selected via a jumper (JP10) instead of the internal quartz oscillator CLOCK OUT outputs NIM/TTL LEMO two 50 MHz reference clock outputs; one TTL 50-Ohm driver and one NIM driver LTC rollover output TTL P2 VME backplane Local time clock rollover bit for 'raw-mode' GPS time referencing, selectable by jumpers (JP6) to go to the VME-SG board via the VME P2 connector (pin C14 = LTC rollover bit). Event Number inputs RS485 17x2-pin header 16-bit translated event number from the ENT module. pin 1/2 pin 3/4 : pin 31/32 pin 33/34 = +/- event number output bit 0 = +/- event number output bit 1 : = +/- event number output bit 15 = +/- "Global" trigger G.TRG OUT output TTL LEMO Global Trigger fan-out (monitor) from Event Number bus Extended Event Bits outputs RS485 5x2-pin header extended event number bits 16-19. Pin configuration: 1/2 = +/- event number bit 16 3/4 = +/- event number bit 17 5/6 = +/- event number bit 18 7/8 = +/- event number bit 19 9/10 = [not used] AUX OUT output TTL LEMO optional signal output, programmable via VME bus VFI Flags inputs RS485 7x2-pin header 7 flag signals from the VFI module. Pin configuration: 1/2 = +/- Remote Veto Flag (VME programmed veto) 3/4 = +/- Veto Status Flag (combined Trigger Veto) 5/6 = +/- Auxiliary Flag (optional, fixed by jumper JP3 setting) 7/8 = +/- Hut 4 TDC Busy (=BIP4) 9/10 = +/- Hut 3 TDC Busy (=BIP3) 11/12 = +/- Hut 2 TDC Busy (=BIP2) 13/14 = +/- Hut 1 TDC Busy (=BIP1) Spare Flags outputs RS485 5x2-pin header 5 optional flag signals, programmable via VME bus LEDs and their functions 1PPS flashes at each 1-Pulse-Per-Second (1PPS) pulse from the Motorola GPS receiver TX/RX (RCV/UA) 4 LEDs for monitoring the serial data from the GPS receiver (RCV) and UART/front panel (UA) port; two each: TX=transmit and RX=receive Fifo Full goes on if the 64x4K Event FIFO is full, indicating either VME readout too slow or not active. New Data goes on if new data is buffered in the Event FIFO and not read out yet. TRG0,...,TRG3 each flashes with their corresponding input signal TRG0,...,TRG3 Ext. CLK goes on if External Clock input is fed with a clock signal G.TRG flashes at each Global Trigger pulse trensferred through the Event Number Data bus Extended Event Bits 4 LEDs showing the status of the Event Number extension bits 16...19 AUX shows status of AUXiliary output

JP4,...,JP7:	Select trigger signal level of the TRG0,...,TRG3 inputs either NIM or TTL: TTL: pins 1+2 shorted, pins 3 and 4 open, NIM: pins 1+3 shorted, pins 2+4 shorted.
JP8:	Select TRG4 source: TRG4 = Global Trigger (via LTC6-EVT add-on module): pins 1+2 shorted [Default], or: Direct input (TTL) for TRG4: GND = pin 3 or 4, signal = pin 2.
JP9:	Select the LTC rollover bit for GPS 'raw-mode' time stamping by placing a jumper to one of the following labeled positions:   24 = 0.671 seconds (between rising edges)   25 = 1.342 seconds   26 = 2.684 seconds   27 = 5.369 seconds   28 = 10.74 seconds   29 = 21.47 seconds [DEFAULT]   30 = 42.95 seconds   31 = 85.90 seconds
JP10:	Select 50 MHz clock source:   position 1/2 = internal quartz clock oscillator [DEFAULT]   position 2/3 = external clock via Lemo input
JP11,JP12:	Phase select for internal 50 MHz clock signals TCLOCK and WCLOCK - experimental options for minimizing transition errors between LTC and FIFO [Default is "CLK3" (1 + 3 shorted)]: phase=CLK0: phase=CLK1: phase=CLK2: phase=CLK3:
S1:	DIP switch to select TRG 0,...,4 input enable/disable (ON=enable, 1=TRG0, 2=TRG2, etc.) [DEFAULT: all enabled]
S2:	Dip switch to select the upper 8 bits of the base VME address (A24-mode: A16 ... A23 = 0x000000 ... 0xFF0000)

• Setup:
  1. set Serial Port UART to 8N1, 9600 baud (default), and reset all counters and buffers:
     write 0x83A7 to Status Register (base address).
  2. get ready for data acquisition (un-reset):
     write 0x0027 to Status Register (base address).
• GPS serial data readout:
  1. scan Status register (base address) for bit 5 (D5),
  2. if serial RX Fifo "NOT EMPTY" flag is set (D5=1) then:
     • read serial port buffer (base address + 0x02)
       [note: only the lower 8 bits contain data]
     • repeat steps 1-2 above until status bit D5 is 0 again (RX fifo empty)
• Event Trigger Fifo readout:
  1. increment Fifo Read Pointer by writing 0 to its address (base + 0x04),
  2. scan Status register (base address) for bits 7-15,
  3. if any of the Event Trigger Fifo status bits are 1 (D7=full flag, D8-15="NOT EMPTY" flags for byte 0-7) then:
     • read all 4 Event Trigger Fifo sections A-D (base+0x06,...,base+0x0c)
     • repeat steps 1-3 above until all status bits D7-D15 are 0 (all fifo sections empty)
• writing to GPS serial port buffer:
  • write 8-bit word to base address + 0x02 (upper 8 bits unused)
• setting spare digital outputs and AUX output (optional multi-purpose signals at front panel):
  • set output bits high by OR-ing status bits D10...D14 with default Status word (default = 0x0027) and write to Status Register
  • unset output bits to low by AND-ing status bits D10...D14 with default Status word (default = 0x0027) and write to Status Register

• The schematics were edited with ORCAD STD V4 on a Pentium PC.
  • page 1: (gif or postscript) root page,
  • page 2: (gif or postscript) main board overview
  • page 3: (gif or postscript) interface for Motorola Oncore GPS module,
  • page 4: (gif or postscript) trigger input logic,
  • page 5: (gif or postscript) VMEbus logic + power supply,
  • page 6: (gif or postscript) 50 MHz oscillator + 32-bit clock counter,
  • page 7: (gif or postscript) timing diagram,
  • page 8: (gif or postscript) status control + RS232 port for Motorola GPS,
  • page 9: (gif or postscript) trigger event fifo buffer,
  • page 10: (gif or postscript) LTC6-EVT add-on module = event number + hardware flags interface

• The PCB layout was designed with TANGO PCB V2 on a Pentium PC. The module consists of 2 PCB's:
  1. Main motherboard (LTC6-A): 4-layer design
     [drilling and etching service provided by Advanced Circuits]
     • top layer, bottom layer, ground layer, power (VCC) layer, and
     • top silk print layer.
     • gerber files (zipped) and order sheet for first prototype series with Advanced Circuits
  2. EVT add-on board (LTC6-EVT): 2-layer design
     [drilling and etching service provided by UW Physics Electronics shop]
     • top layer, bottom layer, and
     • top silk print layer.

• List of parts needed for production of one board (MS Office97 format)

• LTC6_ADR.TDL (U18 - GAL26CV12B-15LP): VME address logic
• LTC6_CNT.TDL (U20,U21,U26,U27 - GAL22V10D-10LP or PALCE22V10H-10PC/5): 8-bit parallel fast counter (50 MHz), cascaded to 32-bit Local Time Counter with 4 PLDs
• LTC6_TR1.TDL (U7 - GAL22V10D-7LP or PALCE22V10H-7PC/5): 5-channel trigger input register
• LTC6_TR2.TDL (U8 - GAL22V10D-7LP or PALCE22V10H-7PC/5): 5-channel trigger logic for FIFO write, in connection with LTC6_TR1
• UARTCTRL.TDL (U31 - GAL22V10D-15LP or PALCE22V10H-15PC/4): control logic for UART (GPS serial data)

• 10/03/99 - Version 6.0: LTC6 design finalized for etching.

• 11/10/99 - Version 6.1:
  • Transistors Q1 and Q2 each found to have E and C pins reversed in the schematics. Corrected by turning them 180 degrees on the PCB.
  • Signal /DEN disconnected from U18/pin26. Then U16/pin19, U17/pin19 connected to GND [can probably be done in PLD code for LTC6_ADR without modifying the current PCB design].
  • WCLOCK signal terminated with 100 Ohms to GND at U48/pin27.
  • TCLOCK signal terminated with 100 Ohms to GND at U8/pin1.
  • SMD capacitors used for bypass capacitors C60 - C67 (at PLCC sockets for U41 - U48), soldered to bottom layer. Standard thru-hole capacitors won't fit underneath the PLCC socket.

• GAL22V10: Generic Array Logic, PLD, 22 inputs / 10 output cells.
• GAL26CV12: Generic Array Logic, PLD, 26 inputs / 12 output cells.
• HD-6402: Universal Asynchronuous Receiver/Transmitter [UART] (Mil data sheet)
• IDT7203: CMOS Asynchronous FIFO, 2048 x 9-bit
• IDT72241: CMOS Sync FIFO, 4096 x 9-bit (application note)
• LM7905: Negative Voltage Regulator, -5V Output
• MAX232: Dual RS-232 Driver/Receiver, +5V-Powered
• MC10124: Quad TTL to MECL Translator
• MC10125: Quad MECL to TTL Translator
• MC74AC04: Hex Inverter, 24mA outputs (TTL 50 Ohm drivers)
• SN74F30: 8-Input NAND Gate
• SN74F244: Octal Buffers/Drivers with 3-State Outputs
• SN74F245: Octal Bus Transceivers with 3-State Outputs
• SN74F574: Octal Edge-Triggered D-Type Flip-Flop (Register) with 3-State Outputs
• SN74HC08: Quad 2-Input AND Gates
• SN74LS221: Dual Monostable Multivibrators with Schmitt-Trigger Inputs
• SN74LS393: Dual 4-Stage Binary Counter
• SN74LS688: 8-Bit Magnitude Comparator
• SN75ALS194: Quad Differential Line Drivers
• SN75ALS195: Quad Differential Line Receivers