FCM circuit addition: Trigger / BIP veto for T0 pulses

In theory, all TDCs should get identical TO (reference trigger) and event number informations. For the average single triggers which occur with the current setup at a rate of about 10 Hz, only one T0 signal will be recorded at each event in a TDC window (16 µsec wide), along with one single event number. This event number is always identical with the one latched by the Struck module.

But in practice, there are occasional cases where more than one trigger will occur during a TDC event window. In most cases, the first T0 / event number data in this sequence is corresponding to what the Struck latch is recording, i.e. the trigger that caused the Common Stop Trigger for the TDC modules. At the current setup, the Common Stop Trigger signal is 6 µsec delayed from the causing Global Trigger signal. Thus, in most cases, the first T0 signal in the TDC data should have a time-stamp value of approx. -6000 nsec.

Under very rare circumstances though, the first T0 signal in a TDC window might have been recorded before the -6000 nsec point in the TDC window. The decision/veto circuit in the center hut (see VFI board description) is vetoing Global Triggers as long as any TDC in any Fastbus crate is still busy. Thus the majority of TDCs might be able to record new data again when one of them is still busy buffering the last data. Only when the last TDC is ready again and setting the combined BIP flag back to low, a new Global Trigger will be allowed for a new Struck latch and TDC Common Stop Trigger (STRG and FTRG).

Thus, all T0 triggers should be vetoed, too, whenever the combined BIP flag is set high!

Therefore, the following circuit has been added to the FCM board:

Performance tests of this circuit

a) 4 possible cases

Case 1, example 1: BIP signal low during the entire duration of the Global Trigger pulse = NO VETO. ch.1: Global Trigger, measured at the Lemo connector J2 (NIM level), ch.2: Combined TDC BIP trigger (BIP-OR), measured at the Lemo input conector J7 (TTL level), ch.3: "event number splitter" / t0 reference trigger output signal for the TDCs, measured at the FIV board after a 10 foot "CAL" cable (TTL/RS485 level).

Case 1, example 2: BIP signal low = NO VETO. (same setup as above.)

Case 2: BIP signal high during the entire duration of a Global Trigger pulse = full VETO ! (same setup as above.)

Case 3: BIP signal changing from high to low during a Global Trigger pulse = full VETO ! (same setup as above.)

Case 4: BIP signal changing from low to high during a Global Trigger pulse = partial VETO only! (same setup as above.) This case shows an unavaoidable transition overlapping problem. Fortunately, it won't have any negative effect on the TDC data recording, since the TDCs are already busy for approx. 250 nsec before the BIP signal arrives at the center hut, due to propagation delays mostly in the 125 foot long "BIP" cables. Thus, these partially vetoed trigger signals would not be seen by the TDCs anyway!

b) behavior at bursts of Global Triggers

Pulse sequences during bursts of Global Trigger pulses (example 1): ch.4: (top) Global Trigger at the Lemo input connector J2 (NIM-level), ch.2: (2nd from top) Combined TDC busy signal (BIP-OR), measured at the Lemo connector J4 (TTL-level), ch.1: (2nd from bottom) Trigger reference signal (T0) for the "event number splitter", measured at the modular connector JP1 of the FCM board, including local BIP-veto circuitry, (RS485/TTL level), ch.3: (bottom)Struck Stop Trigger (STRG), measured at Lemo connector J6 (NIM-level). As clearly shown by comparing the channel 1 versus channel 4 pulses, all global triggers during a BIP=high period are vetoed and not forwarded to the Fastbus boards.

Example 2 (same setup as above.)

Example 3 (same setup as above.)