/*************************************************************************/
/*  FCM.TDL                                                              */
/*                                                                       */
/*  Address logic for the FAN-IN/OUT AND CALIBRATION MODULE (FCM) for    */
/*  the VME electronics of the SuperK OD DAQ.                            */
/*  Checks the VME bus for the following conditions:                     */
/*                                                                       */
/*    AS (Address Selector)   = 0                                        */
/*    WR (Write/Read flag)    = 0  (=write)                              */
/*    AM0..5 (Addr. Modifier) = 29 (hex)                                 */
/*    Addresses:                                                         */
/*      16-bit Test Pattern   = D0xx (hex)                               */
/*      Auxiliary Data        = D6xx (hex)                               */
/*      DTACK reply & LED out = D000...D7FF (hex)                        */
/*************************************************************************/

#define  PALNAME FCM
#define  JEDFILE "FCM.JED"
#define  PALTYPE "p22v10"
#define DESIGNER H.G. Berns
#define  COMPANY SuperK group, UW-Physics, Seattle
#define  PARTNUM P22V10
#define REVISION V1.0 (last: July 9, 1996)
#define COMMENTS \
        FCM address selector logic (D0xx...D7FF)

/************ I/O definitions ********************************************/
                                                                         
PALNAME  (in  a15..8,       /* VME bus address bits 8-15                 */
              !as,          /* Addr. Select from VME bus                 */
              !wr,          /* Read/Write flag from VME bus              */
              am1..0;       /* Addr. Modifier bits 0+1                   */
          io  am5..2,       /* Addr. Modifier bits 2-5                   */
              dtack,        /* DTACK output to VME bus                   */
              pat,          /* pulse for test pattern register clock     */
              aux,          /* pulse for auxiliary register clock        */
              led)          /* ackknowledge LED (D000...D7FF)            */

/************ PLD equations **********************************************/
{
    group ad[a15..8], am[am5..0], ins[am5..2], outs[pat, aux, led],
          ad3[a15..11];
    
    outs[].oe     = ~0;     /* enable active outputs                     */
    ins[].oe      = 0;      /* select I/O's as input only                */

    dtack = 0;

    pat = as & wr & am[]==41 & ad[]==208;           /* Addr = D000..D0FF */
    
    aux = as & wr & am[]==41 & ad[]==214;           /* Addr = D600..D6FF */
    
    led = as & wr & am[]==41 & ad3[]==26;           /* Addr = D000..D7FF */
    
    dtack[].oe = as & wr & am[]==41 & ad3[]==26;    /* Addr = D000..D7FF */

/************ PLD part definition ****************************************/

    putpart(PALTYPE, JEDFILE,
     a8,  a9, a10, a11, a12, a13, a14, a15,  as,  wr,   am0, GND,
    am1, am2, am3, am4, am5,   _,   _, led, aux, pat, dtack, VCC);

/************ Test vector(s) *********************************************/

    test (ad[], am[], as, wr => pat, aux, led, dtack) {
       tracef("%3d %2d %w %w => %w %w %w %w",
             ad[], am[], as, wr, pat, aux, led, dtack);

       (  ?, 0,?,? => 0,0,0,\Z); /* Address modifier not equal 0x29 */
       (  ?, ?,1,? => _,_,_, _); /* AS = 1 */
       (  ?, ?,?,1 => _,_,_, _); /* WR = 1 */     
       (  0, ?,?,? => _,_,_, _); /* Addr = 0 */    
       
       (206,41,0,0 => _,_,_, _);
       (207, _,_,_ => _,_,_, _);
       (208, _,_,_ => 1,_,1, 0); /* D0xx  ==> Pattern register clock */
       (209, _,_,_ => 0,_,_, _);
       (210, _,_,_ => _,_,_, _);
       (211, _,_,_ => _,_,_, _);
       (212, _,_,_ => _,_,_, _);
       (213, _,_,_ => _,_,_, _);
       (214, _,_,_ => _,1,_, _); /* D6xx  ==> Auxiliary register clock */
       (215, _,_,_ => _,0,_, _);
       (216, _,_,_ => _,_,0,\Z);
       (217, _,_,_ => _,_,_, _);
       (218, _,_,_ => _,_,_, _);
       (219, _,_,_ => _,_,_, _);
       (220, _,_,_ => _,_,_, _);
       (221, _,_,_ => _,_,_, _);
       (222, _,_,_ => _,_,_, _);
       (223, _,_,_ => _,_,_, _);
       (224, _,_,_ => _,_,_, _);
       (225, _,_,_ => _,_,_, _);
    }                     
}

/************ end of TDL file *********************************************/