Fast FSCC Reset Setup

From an email message sent to Jordan Goodman Aug. 11, 1996, in reply to his message from Aug. 10, 1996:

On Sat, 10 Aug 1996, Jordan Goodman wrote:
> As you are having problems with the auto reset, we would be happy with a
> "manual" test. If you cause a mismatch, but do not abort the run - then
> manually send the reset signal and then after a second or two send the
> trigger hold then release the reset signal and the then the trigger hold
> this should test things out. (By manual, I mean with a pulse generator or
> something equivalent)...
> Jordan

Date: Sun, 11 Aug 1996 11:21:49 +0900 (JST)
From: Hans-Gerd Berns <berns@sukai09e>
To: Jordan Goodman <goodman@umdgrb.umd.edu>
Cc: superk electronics <skelec@katherine.physics.UMD.EDU>
Subject: Re: Test of FSCC reset code

Hi Jordan,
hmmm, kinda tricky with a pulse generator, but not impossible.
I haven't thought of putting a veto signal from an external pulser (or
pushbutton or so), so therefore it's not implemented with the new
boards. But I actually like the idea. There's still room to add a
cable and change a PLD quickly to OR the external signal with the other
veto signals. I'll prepare the spare for this purpose today.
Just to be sure we're agreeing on the same timing for the 'fast reset'
signal and the veto (trigger hold) signal, this is how I will program
the pulser:

             _     _    _       _                                      _
TSTRB (*)  _| |___| |__| |_____| |____________________________________| |
                      ___________________________
Fast Reset __________|                           |_______________________
                                    ___________________________
Veto       ________________________|                           |__________

                     |<-- 1 sec -->|<-- 1 sec -->|<-- 1 sec -->|

(*) = Trigger strobe at the FSCC TSTRB input, caused by the trailing edge of a TDC BIP signal.

So, the Fast Reset pulse is 2 seconds long. During the 1st second, triggers
to the TDCs and Struck latches are not vetoed so that a few FSCC trigger
strobes will come through after each BIP. This way, the FSCC will be
able to read the input port a couple of times and detect that the trigger
ID code has changed from 0x0 to 0x1. Then triggers will be vetoed to
keep the TDC buffers aligned before the Fast Reset signal is released again.

Does this sound ok?
- Hans