SuperK OD custom electronics overview

rev. HGB 03/31/97

This is a brief overview of the current version of the SuperK customs electronics made by the University of Washington group for the outer detector data acquisition (OD-DAQ). The last upgrade (version 2) was performed August 01, 1996.

Click here for a clickable map of the OD-DAQ electronics.

There is also a more detailed inventory list available, including all electronics items and cables by the University of Washington group.

For other OD DAQ custom electronics modules - e.g. the Front-End QTC Module made by the BU collaboration group - and for further documentation please check Ken Young's comprehensive OD DAQ description.

This document is divided into the following sections:

Fastbus electronics (outer electronics huts)
VME electronics (central electronics hut)

a) custom modules inside the VME crate
b) LED status display box
c) Table of data and flag inputs at the Fifo modules (CAEN V533)
OD hardware revision history
Other OD DAQ electronics documentation

Note: This site is best viewed with Netscape Navigator V2 or compatible!

Fastbus electronics (outer electronics huts)

Click on any module of this map to learn more about it:

FB crate front

In each outer quadrant electronics hut are 3 racks - mounted next to each other - reserved entirely for the outer detector front-end electronics. The Fastbus crate sits in the middle of these 3 racks, and its modules are responsible of forwarding digitized data from the approx. 460-475 OD PMTs of this quadrant to the central electronics racks. There, the data will be merged with the data from the other 3 quadrants, time-stamped and then collected by the workstation network in the control room for further handling.

An overview drawing of the cabling between the Fastbus modules is shown here. Also, a photo of the rear side view of the FB crate are available.

Fastbus crate arrangement:

slot no.	module name	function
1	FIV	Fastbus Interface to VME: This custom board provides trigger and control signals between the the OD DAQ VME electronics in the central electronics hut and the Fastbus modules. It also provides proper handling of the 16-bit "event number", distributed via the EVENT COUNT DRIVER boxes in the center of the outer huts, to the TDC and Struck latch modules.
7	Struck Latch	Struck mod. STR137: 128-channel input latch: Latches the 16-bit "event number" with each Common Stop Trigger.
9	TDC	LeCroy mod. 1877: 96-channel Time-to-Digital Converter: Reads the QTC pulses of the PMT channels 0...95 in 0.5 nsec resolution and saves them in a up to 32 µsec wide buffer after each Common Stop Trigger - which is then read by the FSCC controller. Currently the buffer window width is set to 16 µsec.
11	TDC	dito as slot 9, but reads QTC pulses of PMT channels 96...191.
13	TDC	dito as slot 9, but reads QTC pulses of PMT channels 192...287.
15 (1)*	TDC	dito as slot 9, but reads QTC pulses of PMT channels 288...383.
17	TDC	dito as slot 9, but reads QTC pulses of PMT channels 384...494 and reference triggers along with "splitted" event number bits: input channel 91 = global trigger reference (=T0), input channels 92...95 = "splitted" event number bits 0...3
21 (2)*	FSCC	BiRa mod. 9101: Fastbus Smart Crate Controller with Fermilab modifications (version PC4b): Runs VxWorks software controlled via ethernet by the "sukant" workstation in the center hut. After each Common Stop Trigger the FSCC waits a few µseconds for a strobe signal from the FIV module, indicating that the TDCs have buffered new data. It then reads out the TDC buffers and the corresponding eventnumber from the Struck latch and transfers them via 32-bit RS485 cables to the VME crate in the center hut.
21 (2)* (rear)	AUX card	Bira mod. FBA-771: 32-bit RS485 FSCC Auxiliary interface (also labeled as Fermilab model DARTAC): 32-bit differential TTL (RS485) driver for the fast data stream from the FSCC to the DC2/DM115 modules in the center hut VME crate.
underneath crate	Fan Tray	Comair-Rotron cooling fan tray model MB1000-800: needed for sufficient cooling of the Fastbus modules. Please make sure it's running!
rack bottom	Power supply	Fastbus power supply (modified SLAC model MK-II): Provides high-current DC voltages for the Fastbus crate. This supply requires manual operation, e.g. after a power failure the Reset button needs to be pushed before the ON circuit breaker can be pushed... If any of the voltages are out of their valid operating range, the user will hear a loud waring beeper at approx. 1 second intervals at the FIV module.
where: (1): except hut 3 = slot 16, (2): except hut 3 = slot 23

VME electronics (central electronics hut)

a) custom modules inside the VME crate

Click on any module of this map to learn more about it:

VME crate front

The OD DAQ VME crate (front photo and rear photo) is mounted into one of the two outer detector electronics racks (photo) in the center hut. The modules in this crate are responsible for:

distributing Common Stop Trigger pulses from the VME-TRG module to the OD front-end electronics in the outer huts,
receiving and buffering digitized OD PMT pulses and status signals (e.g. TDC busy/deadtime) from the 4 outer huts' Fastbus crates,
tagging all OD PMT data with "event numbers" - provided externally by the VME-TRG module - and time-stamps - provided by a 32-bit local time clock and a UTC/GPS receiver interface,
controlled and directly interfaced by the "sukant" workstation which is responsible for integrating the OD data with the inner detector (ID) data as part of the SuperK computer network.

Four of the modules in this VME crate are special-purpose boards and their locations and intercabling with the other commercial modules are sketched here:

VME crate arrangement:

slot no.	module name	function
1	Bit3	Bit-3 model 467-1-202: VME controller interface to sun computer ("sukant").
2	GPS-VME	TrueTime model VME-SG: VME interface for the GPS receiver. Gets the IRIG-B data from the optical fiber receiver at the next slot via the VME backplane. `VME base address: 0xFF00`
3	GPS-fiber	TrueTime model 560-5625: optical fiber receiver for the VME-SG module: Receives the optical fiber signal (IRIG-B code) from the GPS receiver in the radon next to the car tunnel entrance and converts it to RS485 pulses for the VME-SG module. The green LED indicates by bright pulsing that the signal is ok. If the LED is dim please check whether the optical fiber cable is properly connected or whether the receiver in the radon hut has been accidentally shut off.
4	LTC	Local Time Clock: Custom board that provides 20 nsec accurate local time (in reference to the GPS clock) and trigger and reference clock handling for the Fifo (V533) modules.
5	Fifo 0	CAEN mod. V533: 32-bit Fifo module: This module latches the 32-bit local time at each Global Trigger and End-of-BIP (TDC Busy-in-Progress) pulse in order to time-stamp OD PMT data and measure the OD-DAQ deadtimes. [In a future upgrade, the time-stamping and dead-time measurements will be separated, so this module will only be triggered by the global triggers.] `VME base address: 0xF10000`
6	Fifo 2	Dito as slot 5. Currently, this module is set up exactly as in slot 5 and works as a backup unit only. In a future upgrade, it will be used for measuring TDC deadtimes only, buffering the local time at the trailing edges of TDC BIP pulses. `VME base address: 0xF20000`
7	VFI	VME-Fastbus Interface: This custom board contains delay and veto logic for the Fastbus TDC/latch trigger, control (reset/clear) and feedback signals transmitted via 125 feet long cables to the outer electronics huts. It also provides the signals for the LED status display box (on top of the VME crate).
8	Fifo 1	Dito as slot 5. This module latches event numbers and OD status flags (TDC BIPs, Veto, etc.) at each incoming Global Trigger. `VME base address: 0xF00000`
9	ENT	Event Number Translator: Custom board to interface between the EVENT COUNT DRIVER in the trigger electronics rack and the OD-DAQ. It also contains a NIM fanin/out driver for the 'global trigger' signal, provided by the VME TRG module.
12	FCM	Fanin/out and Calibration Module: This custom board is an additional interface between the VME crate and the Fastbus electronics, transceiving additional trigger, control and test pulses via 125 feet cables to/from the outer electronics huts.
14	DPM-1	MicroMemory mod. 6390/32: 32MB Dual Port Memory: In conjunction with the DPM board in the neighboring slot 15 it buffers fast data streams from the Fastbus FSCC of hut 1, received and controlled by the DC2/DM115 module in slot 15 of the rear section of the VME crate. VME address range: 0x08000000 ... 0x09FFFFFF
15	DPM-2	Dito as slot 14, but VME address range: 0x0B000000 ... 0x0CFFFFFF
15 rear	DC2-1	Access Dynamics mod. DC2/DM115 (with Fermilab modifications): Smart interface receiver for the 32-bit fast data stream from the Fastbus of hut 1, and "ping-pong" controller for the DPM boards in slot 14 and 15 via a VSBbus overlay module.
16	DPM-3	Identical setup as for slots 14, 15, and 15 rear, but for receiving and buffering of Fastbus data of hut 2.	VME address range: 0x0E000000 ... 0x0FFFFFFF
17	DPM-4		VME address range: 0x11000000 ... 0x12FFFFFF
17 rear	DC2-2		VSBbus overlay at rear slots 16+17.
18	DPM-5	Identical setup as for slots 14, 15, and 15 rear, but for receiving and buffering of Fastbus data of hut 3.	VME address range: 0x14000000 ... 0x15FFFFFF
19	DPM-6		VME address range: 0x17000000 ... 0x18FFFFFF
19 rear	DC2-3		VSBbus overlay at rear slots 18+19.
20	DPM-7	Identical setup as for slots 14, 15, and 15 rear, but for receiving and buffering of Fastbus data of hut 4.	VME address range: 0x1A000000 ... 0x1BFFFFFF
21	DPM-8		VME address range: 0x1D000000 ... 0x1EFFFFFF
21 rear	DC2-4		VSBbus overlay at rear slots 20+21.
top	LED Box	LED status display box: see description below

	Note: Almost all of the VME modules are assigned for a specific slot in the VME crate due to interconnections on the rear backplane. Some of those interconnections carry supply voltages capable of high currents (3-5 Amps or more).
	Thus, moving any of the boards to a different slot than assigned might result in destruction of either the board(s) or the VME crate backplane !!

	Also: Check out some important notes about the Fifo or DPM boards before you install a new or replace the old ones with new ones.

b) LED status display box

The LED status display box is placed on top of the VME crate, and it is used for visual debugging of possible hardware problems with the OD DAQ. The following is displayed:

Fifo VME Busy:: should be dark during normal detector runs. A orange light is indicating that the online software either can't keep up with the trigger rate of the detector or is halted.
Trigger OK:: If this (green) LED is flashing synchronously with the trigger rate, then everything is OK. This indicates that the TDC modules in the outer huts are getting triggers. It stays dark during any veto condition.
Veto on:: During normal operations this (red) LED will flash synchronously with the "Trigger OK" LED. It will be steady on - indicating that TDC/latch triggers will be blocked - whenever a veto condition is programmed by the online software or caused by a "TDC busy" condition.
TDC Busy Hut #:: 4 red LEDs (one for each outer hut) indicate the momentary TDC busy conditions. Under normal conditions these LEDs will all synchronously flash with the "Trigger OK" LED. If one of them stays steadily on it means that one of the TDC modules is not working properly. In most cases a FSCC reset clears it again. In some severe cases the power supply for Fastbus crate with the problem module needs to be turned off for a few seconds and then turned on again.

c) Table of data and flag inputs at the Fifo modules (CAEN V533)

Fifo #	VME slot	base address	trigger input	data input bits	data / flag name
0	slot 5	`0xF10000`	G + B ()*	0...31	Local Time
1	slot 8	`0xF00000`	G + B ()*	0...15	Event Number
				16	global trigger (long) (3)*
				17	End-of-BIP flag
				18	GPS fine-tune flag (4)*
				19	global trigger (40 nsec) flag
				20...23	BIP hut 1...4 (inverted)
				24	AUX bit (4)*
				25	Veto flag (inverted)
				26	Reset Veto flag (inverted)
				27...31	-- free / not used yet --
2	slot 6	`0xF20000`	G + B ()*	0...31	Local Time (2)*

where

(*)
= Global Triggers combined (OR) with End-of-BIP Triggers.
(*2)
= In the future, this will be dedicated to time-stamp the End-of-BIP Triggers only, in order to measure the TDC deadtimes. Currently, this fifo is only used for backup of Fifo 0.
(*3)
= This is the original trigger signal from the Event Number cable (17th bit), as originated from the EVENT COUNT DRIVER box. It's of approx. 250...350 nsec length.
(*4)
= Not implemented or used yet with the current OD-DAQ version.

OD hardware revision history

Version 1 (Dec. 1995 - Aug.01, 1996) revision history,
Version 2 (Aug.01, 1996 - ) revision history.